1. Field of the Invention
The present invention relates to a semiconductor device including a high withstanding voltage metal oxide semiconductor field effect transistor (MOSFET) and a method of manufacturing the same.
2. Description of the Related Art
Conventionally, various efforts have been made so as to attain high withstanding voltage of a MOSFET. As one example of the efforts, there has been proposed a method of diffusing low concentration impurities in a region adjacent to a drain region or in a part of the drain region, so as to reduce an electric field concentration occurring near a surface of the drain region, which is a one of the factors of withstanding voltage deterioration.
A typical structure of the above-mentioned high withstanding voltage MOSFET is described based on an example of an n-channel type MOSFET using a p-type substrate, with reference to a cross-sectional view illustrated in FIG. 6. A p-type well 2 is formed along a main surface of a p-type semiconductor substrate 1. The p-type well region 2 is doped with low concentration n-type impurities so that a low concentration source region 3 and a low concentration drain region 4 are formed therein. Further, the low concentration source region 3 and the low concentration drain region 4 are doped with high concentration n-type impurities so that a high concentration source region 5 and a high concentration drain region 6 are formed therein, respectively. Above a surface of the substrate on which the low concentration source region 3 and the low concentration drain region 4 described above are formed, a gate electrode 9 is formed through a gate oxide film 7 and a field insulating film 8. In this manner, the MOSFET is formed. In the MOSFET with such a structure, a field concentration occurring near the surface of the drain region when a drain voltage is applied can be alleviated by depletion of the low concentration source region 3 and the low concentration drain region 4, which are formed by diffusing the low concentration n-type impurities. Thus, the high withstanding voltage is attained. However, the low impurity concentrations of the low concentration source region 3 and the low concentration drain region 4 induce reduction in impurity concentrations of the low concentration source region 3 and the low concentration drain region 4 in boundary portions with the adjacent p-type well region 2, with the result that a depletion layer is excessively widened, and hence there is a problem that a short channel effect is increased.
In view of the above-mentioned problem, a trench gate type high withstanding voltage MOSFET in which the short channel effect is suppressed is proposed (for example, see JP 2008-166717 A).
A structure of the above-mentioned trench gate type high withstanding voltage MOSFET is described based on an example of an n-channel type MOSFET using a p-type substrate, with reference to a cross-sectional view illustrated in FIG. 7. A p-type well region 10 is formed on a p-type semiconductor substrate (not shown). The p-type well region 10 is doped with n-type impurities so that a drift region 11 is formed therein. Further, on the drift region 11 described above, a source region 12 and a drain region 13 are formed so as to extend onto element isolation regions 14 by diffusing n-type impurities higher in concentration than that of the drift region 11. A groove-like trench is formed between the source region 12 and the drain region 13, and above the groove-like trench, a gate electrode 17 is formed through a gate oxide film 15 and a cap oxide film 16. In this manner, the trench gate type high withstanding voltage MOSFET is formed. Since a channel region is formed under a trench portion in the trench gate type high withstanding voltage MOSFET according to JP 2008-166717 A, the drift layer does not extend in a channel direction due to diffusion, to thereby suppress the short channel effect.
However, the process flow becomes complicated and the number of steps increases compared to a manufacturing method for a conventional high withstanding voltage MOSFET, and hence there is a disadvantage in view of cost and manufacturing time since a groove-like trench needs to be formed between the source region and the drain region in the trench gate type high withstanding voltage MOSFET according to JP 2008-166717 A.